Sr Staff Engineer, Design Verification

Short Summary

Sr Staff Engineer, Design Verification with Renesas Electronics. Job Responsibilities Coding of simulation infrastructure using SystemVerilog (UVM) & C/(ARM,RISC-V Assembly) SoC Level verification is a must. Actively involve in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug. Set up UVM verification environment, develop, and…

Key Details

• Position / opportunity: Sr Staff Engineer, Design Verification
• Organization: Renesas Electronics
• Country / coverage: India
• Location: Bengaluru, KA, India
• Work arrangement: On-site
• Opportunity type: Jobs
• Sector: Health
• Compensation: Not specified
• Duration: Not specified
• Start date: 2026-08-10
• Application deadline: Not specified

Description

Job Responsibilities Coding of simulation infrastructure using SystemVerilog (UVM) & C/(ARM,RISC-V Assembly) SoC Level verification is a must. Actively involve in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug. Set up UVM verification environment, develop, and verify self-tested test benches for Mixed Signal chips and sub-circuits. Use and Development of Advanced UVM/mixed-signal simulation techniques to enhance simulation efficiency. Generate Verification Plan from the Specifications using vManager Determine Coverage and design completeness requirements Generate random-constraint tests to cover all customer-use-models Create Assertions, cover-groups, checkers, monitors and automatic reporting Set-up and run regression reports Works diligently to accomplish project goals and meet schedule requirements Job Requirements BSEE (MSEE pref.) or equivalent with 10+ years professional industry experience in Digital multi core SoC verification. Experience in digital Verification. Mixed-signal Verification is plus. UVM testbench creation, writing and implementation is a plus. Proficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus Experience with RN(Real Number)/Digital top-level modeling and verification methodology to speed up simulation (understanding accuracy/speed tradeoff and interfaces) Must be able to work independently with limited supervision and work closely with team. Work from office. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .

Responsibilities

• Job Responsibilities Coding of simulation infrastructure using SystemVerilog (UVM) & C/(ARM,RISC-V Assembly) SoC Level verification is a must.
• Actively involve in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug.
• Set up UVM verification environment, develop, and verify self-tested test benches for Mixed Signal chips and sub-circuits.
• Use and Development of Advanced UVM/mixed-signal simulation techniques to enhance simulation efficiency.
• Generate Verification Plan from the Specifications using vManager Determine Coverage and design completeness requirements Generate random-constraint tests to cover all customer-use-models Create Assertions, cover-groups, checkers, monitors and automatic…
• Experience in digital Verification.

Requirements / Eligibility

• Generate random-constraint tests to cover all customer-use-models Create Assertions, cover-groups, checkers, monitors and automatic reporting Set-up and run regression reports Works diligently to accomplish project goals and meet schedule requirements Job…
• Experience in digital Verification.
• UVM testbench creation, writing and implementation is a plus.
• Proficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus Experience with RN(Real Number)/Digital top-level modeling and verification methodology to speed up simulation (understanding accuracy/speed tradeoff and…
• Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier .

How To Apply

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