Principal Package Design Engineer

Short Summary

Principal Package Design Engineer with Renesas Electronics. We are seeking a Senior Advanced Packaging Engineer to lead the development and integration of next-generation packaging solutions for high-performance semiconductors and electronic products. This role will focus on advanced package architectures, assembly processes, thermal and mechanical reliability, and cross-functional collaboration with design, manufacturing…

Key Details

• Position / opportunity: Principal Package Design Engineer
• Organization: Renesas Electronics
• Country / coverage: United States
• Location: San Jose, CALIFORNIA, United States
• Work arrangement: On-site
• Opportunity type: Jobs
• Sector: Information Technology
• Compensation: Not specified
• Duration: Not specified
• Start date: 2026-09-30
• Application deadline: Not specified

Description

We are seeking a Senior Advanced Packaging Engineer to lead the development and integration of next-generation packaging solutions for high-performance semiconductors and electronic products. This role will focus on advanced package architectures, assembly processes, thermal and mechanical reliability, and cross-functional collaboration with design, manufacturing, suppliers, and quality teams. The ideal candidate has deep expertise in semiconductor packaging technologies and a strong track record of bringing complex products from concept through qualification and high-volume production. Responsibilities Lead the design, development, and qualification of advanced semiconductor packaging solutions, including: Flip-chip, Chip Embedding Wafer-level packaging (WLP/FOWLP) Panel-level packaging (laminate, molding) 2.5D/3D packaging System-in-package (SiP) Ball grid array (BGA/CSP) Define package architecture based on electrical, thermal, mechanical, reliability, and cost requirements. Drive package technology selection and development for new product introductions. Work closely with IC design, substrate, board, thermal, reliability, and manufacturing teams to ensure package compatibility and performance. Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy. Perform and guide simulations and analysis related to: Signal integrity / power integrity Thermal performance Mechanical stress / warpage Design for manufacturability (DFM) Develop assembly flows and process requirements for OSATs and manufacturing partners. Lead package qualification activities, including DOE planning, failure analysis, and reliability testing. Resolve packaging-related issues during NPI prototype builds, qualification, and production ramp. Collaborate with suppliers and internal/external manufacturing partners on process improvements, material evaluation, and yield optimization. Create and maintain package specifications, design rules, process documentation, and technical reports. Mentor junior engineers and provide technical leadership across packaging initiatives. Required MSc or PhD degree in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or related field. 5+ years of experience in semiconductor packaging or advanced electronics packaging. Strong knowledge of advanced packaging technologies, materials, and assembly processes. Experience with package reliability testing and qualification standards. Deep understanding of thermal, mechanical, and electrical interactions in package design. Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains. Ability to troubleshoot packaging failures and drive root cause/corrective action. Strong project leadership and cross-functional communication skills. Preferred Master’s or PhD in a relevant engineering discipline. Experience with power semiconductor devices and packaging including Si/SiC/GaN MOSFETS, Power Modules, Intelligent Power modules and their applications in consumer and industrial, automotive, performance computing.computing, AI/ML hardware or mobile products. Hands-on experience with tools for package design and simulation such as: Cadence Allegro Package Designer Solid works ANSYS COMSOL JMP / Minitab Knowledge of JEDEC standards, IPC standards, and semiconductor qualification methods. Experience in W2W, D2W, D2D 3D heterogeneous integration and chiplet-based packaging. The base salary range $195,000 – $240,000 represents the good faith estimate of the hourly wage or salary range that the company reasonably expects to pay for this position at the time of hire. Actual compensation decisions are based on a variety of factors, including but not limited to geographic location, relevant experience, skillset, and internal equity. Additional bonus opportunities are available for this role. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial…

Responsibilities

• We are seeking a Senior Advanced Packaging Engineer to lead the development and integration of next-generation packaging solutions for high-performance semiconductors and electronic products.
• This role will focus on advanced package architectures, assembly processes, thermal and mechanical reliability, and cross-functional collaboration with design, manufacturing, suppliers, and quality teams.
• The ideal candidate has deep expertise in semiconductor packaging technologies and a strong track record of bringing complex products from concept through qualification and high-volume production.
• Responsibilities Lead the design, development, and qualification of advanced semiconductor packaging solutions, including: Flip-chip, Chip Embedding Wafer-level packaging (WLP/FOWLP) Panel-level packaging (laminate, molding) 2.5D/3D packaging…
• Drive package technology selection and development for new product introductions.
• Work closely with IC design, substrate, board, thermal, reliability, and manufacturing teams to ensure package compatibility and performance.

Requirements / Eligibility

• Responsibilities Lead the design, development, and qualification of advanced semiconductor packaging solutions, including: Flip-chip, Chip Embedding Wafer-level packaging (WLP/FOWLP) Panel-level packaging (laminate, molding) 2.5D/3D packaging…
• Drive package technology selection and development for new product introductions.
• Work closely with IC design, substrate, board, thermal, reliability, and manufacturing teams to ensure package compatibility and performance.
• Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy.
• Perform and guide simulations and analysis related to: Signal integrity / power integrity Thermal performance Mechanical stress / warpage Design for manufacturability (DFM) Develop assembly flows and process requirements for OSATs and manufacturing partners.

How To Apply

Use the Apply now button and follow the instructions on the application page.