Principal Firmware/Middleware Engineer

Short Summary

Principal Firmware/Middleware Engineer with Renesas Electronics. As the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. In this high-impact role, you will bridge the gap between cutting-edge silicon (ASICs) and…

Key Details

• Position / opportunity: Principal Firmware/Middleware Engineer
• Organization: Renesas Electronics
• Country / coverage: United States
• Location: San Jose, CALIFORNIA, United States
• Work arrangement: On-site
• Opportunity type: Jobs
• Sector: Health
• Compensation: Not specified
• Duration: Not specified
• Start date: 2026-08-13
• Application deadline: Not specified

Description

As the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. In this high-impact role, you will bridge the gap between cutting-edge silicon (ASICs) and upper-layer cluster orchestration software. You will define how firmware manages complex scale-up topologies, ensures raw hardware performance (maximizing bandwidth and minimizing latency), and maintains absolute reliability across thousands of connected AI accelerators. 1. Architectural Definition & Design Fabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC. Hardware-Software Co-Design: Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware-software interfaces, registers, scratchpads, and memory maps. Protocol Implementation: Define the firmware stack to support UALink physical, link, and transport layers, managing credits, routing tables, and flow control. 2. Initialization, Boot, & Fabric Management Link Initialization & Training: Design deterministic, fast link-training state machines to bring up ultra-high-speed die-to-die and chassis-to-chassis UALink connections. Topology Discovery & Routing: Architect efficient algorithms for runtime topology discovery, dynamic routing, and credit management to prevent fabric congestion. Platform Orchestration: Lead the design of SDKs and APIs that expose switch functionality to baseboard management controllers (BMCs) using OpenBMC and Redfish APIs. 3. Performance, RAS, & Security Latency & Bandwidth Optimization: Fine-tune bare-metal execution paths to guarantee deterministic low latency for collective communication primitives (e.g., All-Reduce, All-to-All). Advanced RAS (Reliability, Availability, Serviceability): Design robust error-handling, telemetry, and fault-isolation micro-architectures (e.g., link degradation fallback, FEC, and error containment). Security & Root of Trust: Implement secure boot, cryptographic firmware authentication, and runtime attestation to ensure fabric integrity. Education & Experience Degree: Bachelor’s or Master’s/Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline. Experience: 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development. Technical Skill Set Language Masteries: Expert-level proficiency in C for bare-metal and RTOS environments (e.g., ThreadX, FreeRTOS, Zephyr) and Python for hardware automation and modeling. Protocol Expertise: Deep technical understanding of high-speed scale-up/scale-out interconnect protocols (UALink, NVLink, CXL, or PCIe Gen5/Gen6). Network Switching Concepts: Comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management. Tooling: Strong familiarity with hardware debuggers (JTAG, Lauterbach Lauterbach/TRACE32) and lab equipment (Oscilloscopes, PCIe/Protocol Analyzers). The expected annual pay range for this position is $230,000-$270,000K. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits…

Responsibilities

• As the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster…
• In this high-impact role, you will bridge the gap between cutting-edge silicon (ASICs) and upper-layer cluster orchestration software.
• You will define how firmware manages complex scale-up topologies, ensures raw hardware performance (maximizing bandwidth and minimizing latency), and maintains absolute reliability across thousands of connected AI accelerators.
• Architectural Definition & Design Fabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC.
• Hardware-Software Co-Design: Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware-software interfaces, registers, scratchpads, and memory maps.
• Protocol Implementation: Define the firmware stack to support UALink physical, link, and transport layers, managing credits, routing tables, and flow control.

Requirements / Eligibility

• Experience: 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development.
• Technical Skill Set Language Masteries: Expert-level proficiency in C for bare-metal and RTOS environments (e.g., ThreadX, FreeRTOS, Zephyr) and Python for hardware automation and modeling.
• Protocol Expertise: Deep technical understanding of high-speed scale-up/scale-out interconnect protocols (UALink, NVLink, CXL, or PCIe Gen5/Gen6).
• Network Switching Concepts: Comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management.

How To Apply

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