DMS Verification Engineer

Short Summary

DMS Verification Engineer with Bosch Group. We are seeking an experienced DMS (Directed Mixed-Signal) Verification Engineer based in Valencia to join our engineering team. In this role, you will collaborate closely with system architects and analog/digital designers to develop and execute comprehensive verification strategies for state-of-the-art Mixed-Signal SoCs. Key Responsibilities: Drive specification reviews to…

Key Details

• Position / opportunity: DMS Verification Engineer
• Organization: Bosch Group
• Country / coverage: Spain
• Location: València, VC, Spain
• Work arrangement: On-site
• Opportunity type: Jobs
• Sector: Information Technology
• Compensation: Not specified
• Duration: Not specified
• Start date: 2026-09-03
• Application deadline: Not specified

Description

We are seeking an experienced DMS (Directed Mixed-Signal) Verification Engineer based in Valencia to join our engineering team. In this role, you will collaborate closely with system architects and analog/digital designers to develop and execute comprehensive verification strategies for state-of-the-art Mixed-Signal SoCs. Key Responsibilities: Drive specification reviews to generate initial verification plans using Vmanager. Define verification strategies, including optimal partitioning between DMS and DV, and model versus schematic equivalence. Plan and manage resources, schedules, and progress tracking, identifying and addressing potential showstoppers. Implement verification plans, run regressions, and track functional and code coverage. Verify the accuracy and performance of behavioral models against circuit-level simulations and measurements. Perform root-cause analysis and debug issues down to RTL, gate, and schematic levels. Maintain and improve functional verification infrastructure, flows, and UVM methodologies. Provide technical leadership, mentorship, and support across multi-site engineering teams. Bachelor's or Master's degree in Electrical/Electronic Engineering, Telecommunications, Computer Science, or a related field. Proven experience in developing validation plans, analyzing test results, and debugging failures at RTL, gate, and schematic levels. Strong working knowledge of SystemVerilog/Verilog and UVM. Experience setting up, running, and debugging Gate-Level Simulations (GLS). Good understanding of DSP techniques and analog schematics. Strong problem-solving, communication, and teamwork skills. Professional working proficiency in English (C1 level minimum). Valid work authorization for the European Union is required. Preferred / Bonus Skills: Experience with System Modeling or Formal Verification. Proficiency in scripting languages such as Python, Make, or Shell. Diversity is an integral part of our corporate strategy and is anchored as one of our values in the “We are Bosch” mission statement. For us, diversity is reflected in the uniqueness of our associates, their personalities, experiences and perspectives. By including everyone and ensuring equal opportunities we unleash our full potential. We are dedicated to ensuring that our hiring processes are fair, inclusive, and free from bias. We are committed to hiring individuals regardless of culture, generation, race, religion an belief, neurodiversity, gender identity, sexual orientation, or disabilities.

Responsibilities

• We are seeking an experienced DMS (Directed Mixed-Signal) Verification Engineer based in Valencia to join our engineering team.
• In this role, you will collaborate closely with system architects and analog/digital designers to develop and execute comprehensive verification strategies for state-of-the-art Mixed-Signal SoCs.
• Key Responsibilities: Drive specification reviews to generate initial verification plans using Vmanager.
• Define verification strategies, including optimal partitioning between DMS and DV, and model versus schematic equivalence.
• Plan and manage resources, schedules, and progress tracking, identifying and addressing potential showstoppers.
• Implement verification plans, run regressions, and track functional and code coverage.

Requirements / Eligibility

• Verify the accuracy and performance of behavioral models against circuit-level simulations and measurements.
• Perform root-cause analysis and debug issues down to RTL, gate, and schematic levels.
• Maintain and improve functional verification infrastructure, flows, and UVM methodologies.
• Provide technical leadership, mentorship, and support across multi-site engineering teams.

How To Apply

Use the Apply now button and follow the instructions on the application page.